The present invention relates to plasma processing, particularly to plasma processing in the production of a semiconductor integrated circuit device.
In the manufacturing process for semiconductor integrated circuit devices there are various plasma chemical reactions. For example, plasma etching and plasma CVD (Chemical Vapor Deposition) have already been established as manufacturing techniques for semiconductor integrated circuit devices.
According to the plasma processing, reaction gas is discharged under reduced pressure to generate such reaction seed as electrons, ions and radicals, which are not stable under atmospheric pressure, thereby accelerating a predetermined chemical reaction to effect the aforesaid etching or CVD. The plasma processing can be a low-temperature process, a dry process, etc. and this is very desirable in the manufacture of semiconductor integrated circuit devices.
In the case of plasma processing, however, since the processing is carried out by utilizing a chemical reaction, dust particles, for example reaction product, are produced during the processing, and such dust particles are deposited on a semiconductor wafer and the inner wall of a processing chamber in the plasma processing equipment. It is known that this causes various problems.
For example, in the case of patterning a laminate film by plasma etching, separate processing chambers are sometimes used for upper and lower layers of the laminate film, that is, patterning is performed twice, separately, in view of the difference of etching gases, etc. In this case, dust particles deposited on a semiconductor wafer during the plasma etching of the upper layer undesirably act as an etching mask (hereinafter referred to simply as "mask") in the plasma etching of the lower layer, thus causing various problems, for example change in shape and size of pattern and short-circuit of the conductor patterns in the longitudinal and transverse directions.
For example, in Japanese Patent Laid Open Nos. 20321/87 and 258048/90 there are described techniques for removing dust particles in plasma processing.
According to the technique described in the Japanese Patent Laid Open No. 20321/87, a reaction product collector capable of moving into a load-lock chamber is disposed around a semiconductor wafer table in a plasma reaction chamber, to remove dust particles produced during plasma processing.
According to the technique described in the Japanese Patent Laid Open No. 258048/90, an electrostatic attractor for the attraction of dust particles is disposed around a semiconductor wafer in a plasma processing chamber to remove dust particles produced during plasma processing.